Chip Verification Will Become a Top Priority

In addition to new design IP, the verification of complex chips will become another challenge. As mentioned earlier, complex chips include more and more subsystems. First, the verification of each subsystem will become more and more challenging as its complexity increases. Secondly, the collaborative work and verification of multiple complex subsystems will become another difficulty in chip verification. Finally, there is heterogeneity in each subsystem in the chip system. For example, high-performance analog/mixed-signal modules (such as memory interfaces, etc.) are increasingly used in complex chip systems, which also brings challenges to the verification of the overall chip system. This poses a challenge because the verification methods for different subsystems are not consistent.

Chip verification first needs to improve efficiency and reduce the time required. In addition, the percentage of successful chip first-time tape-outs is also declining, with as many as 76% of projects requiring two or more tape-outs in 2022 to achieve design goals. Among the reasons why chips need to be taped out multiple times, the first reason is the problem of logic function, and another notable reason is the problem of analog modules: this project will account for 20% in 2020 and 2022, up from 20% a few years ago. It has jumped to 40%, which also shows that the verification related to analog design, and the co-verification of analog modules and other modules will become very important problems to be solved in the field of complex chip verification in the future.

Looking forward to the future, the verification of complex chips first requires a more efficient verification process, such as using a more efficient description language, so as to ensure that chip projects can be delivered on a regular basis. In addition to efficiency, since the logic function is still the primary problem of chip tape-out failure, and as the complexity of the chip system increases, this problem will become more and more serious. Therefore, there are requirements for reliable verification methods, which need to be further reduced. Cost, and improve the support for complex systems, so as to ensure the quality of complex chip systems. Finally, analog verification is expected to become a key link in complex chip systems in the future, including analog verification, as well as co-verification of analog and digital systems (such as analog system modeling into digital system verification, etc.), which is essential for new verification The adoption of methodologies and new EDA systems have created new requirements and are expected to be another major event in the field of verification in the next few years.

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